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| ST7538 POWER LINE FSK TRANSCEIVER s s HALF DUPLEX FREQUENCY SHIFT KEYING (FSK) TRANSCEIVER INTEGRATED POWER LINE DRIVER WITH PROGRAMMABLE VOLTAGE AND CURRENT CONTROL PROGRAMMABLE INTERFACE: - SYNCHRONOUS - ASYNCHRONOUS SINGLE SUPPLY VOLTAGE (FROM 7.5 UP TO 12.5V) VERY LOW POWER CONSUMPTION (Iq=5 mA) INTEGRATED 5V VOLTAGE REGULATOR (UP TO 100mA) WITH SHORT CIRCUIT PROTECTION 8 PROGRAMMABLE TRANSMISSION FREQUENCIES PROGRAMMABLE BAUD RATE UP TO 4800BPS RECEIVING SENSITIVITY 1 mVRMS SUITABLE TO APPLICATION IN ACCORDANCE WITH EN 50065 CENELEC SPECIFICATIONS CARRIER OR PREAMBLE DETECTION BAND IN USE DETECTION PROGRAMMABLE REGISTER WITH SECURITY CHECKSUM MAINS ZERO CROSSING DETECTION AND SYNCHRONIZATION TQFP44 Slug Down ORDERING NUMBER: ST7538P s s s s s WATCHDOG TIMER DESCRIPTION The ST7538 is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and a 5V linear regulator. The device operation is controlled by means of an internal register, programmable through the synchronous serial interface. Additional functions as watchdog, clock output, output voltage and current control, preamble detection, time-out, band in use are included. Realized in Multipower BCDV technology that allows to integrate DMOS, Bipolar and CMOS structures in the same chip. s s s s s s s s BLOCK DIAGRAM DVdd AVdd DVss AVss TEST1 TEST2 TEST3 BU RxFo CD/PD CARRIER DETECTION TEST BU AGC RxD CLR/T PLL DIGITAL FILTER FSK DEMOD IF FILTER FILTER AMPL RAI SERIAL INTERFACE REG/DATA RxTx TxD FSK MODULATOR DAC TX FILTER ALC VOLTAGE CONTROL PLI Vsense ATO ATOP1 ATOP2 + VREG PAVcc Vdc PG XOut XIn WD TOUT RSTO MCLK ZCin ZCout C_OUT CMINUS CPLUS D03IN1407 FILTER CONTROL REGISTER CURRENT CONTROL CL REGOK OSC TIME BASE ZC OP-AMP September 2003 1/30 ST7538 PIN CONNECTION (Top view) REG_DATA C_MINUS REG_OK C_PLUS C_OUT TEST1 35 GND N.C. N.C. 44 43 42 41 40 39 38 37 36 N.C. 34 33 32 31 30 29 28 27 26 25 24 23 PG CD_PD DVSS RXD RxTx TXD GND TOUT CLR/T BU DVDD MCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VDC RAI RXFO TEST2 VSENSE AVDD XIN XOUT SGND ATO CL RSTO TEST3 WD ZCOUT ZCIN N.C. DVSS ATOP1 PAVSS ATOP2 PAVCC D01IN1312 PIN DESCRIPTION N 1 Name CD_PD Type Digital/Output Description Carrier or Preamble Detect Output. "1" No Carrier or Preamble Detected "0" Carrier or Preamble Detected Digital Ground RX Data Output. Rx or Tx mode selection input. "1" - RX Session "0" - TX Session TX Data Input. Substrate Ground (same function as PIN 41) TX Time Out Event Detection "1" - Time Out Event Occurred "0" - No Time-out Event Occurred Synchronous Mains Access Clock or Control Register Access Clock Band in use Output. "1" Signal within the Programmed Band "0" No Signal within the Programmed Band Digital Supply Voltage Master Clock Output Power On or Watchdog Reset Output Test Input. Must be connected to DVss during Normal Operation 2 3 4 DVss RxD RxTx Supply Digital/Output Digital/Input with internal pull-up Digital/Input with internal pull-down Supply Digital/Output 5 6 7 TxD GND TOUT 8 9 CLR/T BU Digital/Output Digital/Output 10 11 12 13 DVdd MCLK RSTO TEST 3 Supply Digital/Output Digital/Output Digital/Input with internal pull-down 2/30 ST7538 PIN DESCRIPTION (continued) N 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name WD ZCOUT ZCIN1 NC DVss ATOP1 PAVss ATOP2 PAVCC CL2 ATO SGND XOUT XIN AVdd Vsense RxFO RAI VDC NC TEST1 REGOK 3 Type Digital/Input with internal pull-up Digital/Output Analog/Input Floating Supply Power/Output Supply Power/Output Supply Analog/Input Analog/Output Supply Analog I/O Analog Input Supply Analog/Input Analog/Input Analog/Output Analog/Input Power floating Digital/Input with internal pull-down Digital/Output Description Watchdog input. The Internal Watchdog Counter is cleared on the falling edges. Zero Crossing Detection Output Zero Crossing AC Input. Must be connected to DVss. Digital Ground Power Line Driver Output Power Analog Ground Power Line Driver Output Power Supply Voltage Current Limiting Feedback. A resistor between CL and AVss sets the PLI Current Limiting Value Small Signal Analog Transmit Output Analog Signal Ground Crystal Output- External Clock Input Crystal Oscillator Input Analog Power supply. Output Voltage Sensing input for the voltage control loop Test Input must be connected SGND Receiving Filter Output Receiving Analog Input 5V Voltage Regulator Output Must Be connected to DVss. Test input. Must Be connected to DVss. Security checksum logic output "1" - Stored data Corrupted "0" - Stored data OK Op-amp Inverting Input. Op-amp Not Inverting Input. Must Be connected to DVss Op-amp Output Substrate Ground (same function as PIN 6) Power Good logic Output "1" - VDC is above 4.5V "0" - VDC is below 4.25V Mains or Control Register Access Selector "1" - Control Register Access "0" - Mains Access Must be connected to DVss. TEST2 37 38 39 40 41 42 C_MINUS4 Analog/Input C_PLUS5 NC C_OUT GND PG Analog/Input floating Analog/Output Supply Digital/Output 43 REG_DATA Digital/Input with internal pull-down NC floating 44 <1> <2> <3> <4> <5> If not used this pin must be connected to VDC Cannot be left floating Cannot be left floating If not used this pin must be connected to VDC If not used this pin must be tied low (SGND or PAVss or DVss) 3/30 ST7538 ABSOLUTE MAXIMUM RATINGS Symbol PAVCC AVdd DVdd AVss/DVss VI VO IO Vsense RAI ATO ATO ATOP1,2 ATOP Tamb Tstg ATOP1 Pin ATOP2 Pin Other pins Power Supply Voltage Analog Supply Voltage Digital Supply Voltage Voltage between AVss and DVss Digital input Voltage Digital output Voltage Digital Output Current Voltage Range at Vsense Input Voltage Range at RAI Input Output Current at ATO Output Voltage range at ATO Output Voltage range at Powered ATO Output Powered ATO Output Current Operating ambient Temperature Storage Temperature Maximum Withstanding Voltage Range Test Condition: CDF-AEC-Q100-002- "Human Body Model" Acceptance Criteria: "Normal Performance" Parameter Value -0.3 to +14 -0.3 to +5.5 -0.3 to +5.5 -0.3 to +0.3 DVss - 0.3 to DVdd +0.3 DVss - 0.3 to DVdd +0.3 -2 to +2 AVss - 0.3 to AVdd+0.3 -AVdd - 0.3 to AVdd +0.3 -2 to +2 AVss - 0.3 to AVdd +0.3 AVss - 0.3 to +PAVcc +0.3 400 -40 to +85 -50 to 150 1500 1000 2000 Unit V V V V V V mA V V mA V V mARms C C V V V THERMAL DATA Symbol Rth-j-amb1 Rth-j-amb2 Parameter Maximum Thermal Resistance Junction-Ambient Steady State(*) Maximum Thermal Resistance Junction-Ambient Steady State(**) TQFP44 with slug 35 50 Unit C/W C/W (*) Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB (**) It's the same condition of the point above, without any heatsinking surface on the board. 4/30 ST7538 ELECTRICAL CHARACTERISTCS (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40C Tamb 85C, unless otherwise specified) Symbol AVCC, DVCC Parameter Supply Voltages DVCC < 4.75V AVCC < 4.75V Test Condition Min. 4.75 0.1 0.1 7.5 Typ. 5 Max. 5.25 1.2 1.2 12.5 10 Transmission & Receiving mode TX mode (no load) RX mode Maximum total current Digital I/O VIH VIL VOH VOL Oscillator VIHX VILX DC Xtal Tclock XtalESR XtalCL Transmitter IATOP Output Transmitting Current in programmable current limiting Vsense connected though a 100pF cap to GND; Rcl=1.85k; RLOAD =1 (as in fig. 13) 250 1.75 1.7 VATO = 2VPP; Fc=86KHz VATO = 2VPP; Fc=86KHz RCL = 1.85k Vsense=0V VAT OP ( A C) PAVcc ----------------------------------- + 7.5V 2 3.5 310 2.3 2.1 -55 -52 4.6 370 3.5 2.5 -42 -49 6 mArms VPP V dB dB Vpp XIN High Level Input Voltage XIN Low Level Input Voltage XTAL Clock Duty Cycle Crystal Oscillator frequency Oscillator Period (1/Xtal) External Oscillator Esr Resistance External Oscillator Stabilization Capacitance External Clock External Clock External Clock 40 16 62.5 40 16 3 2 60 V V % MHz ns Ohm pF High Logic Level Input Voltage Low Logic Level input Voltage High Logic Level Output Voltage IOH= -2mA Low Logic Level Output Voltage IOL= 2mA 3.5 0.4 2 0.8 V V V V 5 30 500 7 50 1000 370 Unit V V V V V/ms mA mArms A mArms PAVCC - DVCC PAVCC and DVCC Relation during Power-Up Sequence PAVCC - AVCC PAVCC and DVCC Relation during Power-Up Sequence PAVcc Power Supply Voltage Max allowed slope during Power-Up AICC + DICC I PAVCC Input Supply Current Powered Analog Supply Current VATO VATODC HD2ATO HD3ATO VATOP(AC) Max Carrier Output AC Voltage RCL = 1.85k Vsense=0V Output DC Voltage on ATO Second Harmonic Distortion on ATO Third Harmonic Distortion on ATO Max Carrier Output AC Voltage for each ATOP1 and ATOP2 pins Output DC Voltage on ATOP1 and ATOP2 pins VATOP(DC) 3.5 4.2 5 V 5/30 ST7538 ELECTRICAL CHARACTERISTCS (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40C Tamb 85C, unless otherwise specified) Symbol HD2ATOP Parameter Second Harmonic Distortion on each ATOP1 and ATOP2 pins Test Condition VATOP = 4VPP No Load VATOP = 4VPP RLOAD =50 (Differential) Carrier Frequency: 132.5KHz HD3ATOP Third Harmonic Distortion on each ATOP1 and ATOP2 pins VATOP = 4VPP No Load. VATOP = 4VPP RLOAD =50 (Differential) Carrier Frequency: 132.5KHz VATOP GST DRNG VCLTH VCLHYST CCLTH CCLHYST VSENSE TRxTx Accuracy with Voltage Control Loop Active ALC Gain Step Control loop gain step ALC Dynamic Range Voltage control loop reference threshold on Vsense pin Hysteresis on Voltage loop reference threshold Current control loop reference threshold on Csense pin Hysteresis on Voltage loop reference threshold VSENSE Input Impedance Carrier Activation Time Figure 16 - 600 Baud Xtal=16MHz Figure 16- 1200 Baud Xtal=16MHz Figure 16- 2400 Baud Xtal=16MHz Figure 16- 4800 Baud Xtal=16MHz TALC Carrier Stabilization Time From STEP 16 to zero or From step 16 to step 31, Tstep Figure 16. Xtal =16MHz Figure 16 Xtal =16MHz 1 500 2 80 100 1 500 77 85 140 2 0.01 0.01 0.01 0.01 Figure 13 Figure 13 Figure 13 Figure 13 1.80 210 170 RCL = 0 -1 0.6 1 30 190 +-19 1.90 250 36 1.6 800 400 200 3.2 2.00 290 210 Min. Typ. -55 -65 Max. -42 -53 Unit dB dB -56 -65 -49 -52 dB dB +1 1.4 GST dB dB mVPK mV V mV K ms s s s ms TST Receiver VIN VIN RIN VCD 200 s Input Sensitivity (Normal Mode) Input Sensitivity (High Sens.) Maximum Input Signal Input Impedance Carrier Detection Sensitivity (Normal Mode) Carrier Detection Sensitivity (High Sensitivity Mode) 2 mVrms Vrms Vrms k mVrms Vrms dB/ Vrms VBU Band in Use Detection Level 6/30 ST7538 ELECTRICAL CHARACTERISTCS (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40C Tamb 85C, unless otherwise specified) Symbol Voltage Regulator VDC Linear Regulator Output Voltage -25 TDCD MCLK CD_PD Propagation Delay Master Clock Output Selectable by register Baud rate BAUD TB Baud rate Bit Time (=1/BAUD) s Zero Crossing Detection ZCDEL Zero Crossing Detection delay (delay between the ZCIN and ZCOUT signals) Figure 19 s 7/30 ST7538 ELECTRICAL CHARACTERISTCS (continued) (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40C Tamb 85C, unless otherwise specified) Symbol ZC(LOW) ZC(HIGH) Parameter Zero Crossing Detection Low Threshold Zero Crossing Detection High Threshold Test Condition Min. -45 5 -20 15 -30 -38 6 see figure 3, 5, 6, 7 & 8 see figure 3, 5, 6, 7 & 8 see figure 3, 5, 6, 7 & 8 see figure 3, 5, 6, 7 & 8 see figure 3, 5, 6, 7 & 8 see figure 3, 5, 6, 7 & 8 see figure 4 TB TB/4 TB/4 TH 7 28 -20 Typ. Max. -5 +45 +20 45 -10 +38 9 5 2 TB/4 2*TB TB/2 TB/2 TB/2 Unit mV mV mV mA mA mV MHz ns ns ZC(OFFSET) Zero Crossing Offset Operational Amplifier COUT(Sync) CIN(Offset) GBWP Ts TH TCR TCC TDS TDH TCRP Max Sync Current Input Terminals OFFSET Gain Bandwidth Product Setup Time Hold Time CLR/T vs. REG_DATA or RxTx CLR/T vs. CLR/T Setup Time Hold Time COUT(Source) Max Source Current Serial Interface 8/30 ST7538 FUNCTIONAL DESCRIPTION Carrier Frequencies ST7538 is a multi frequency device: eight programmable Carrier Frequencies are available (see table 1). Only one Carrier could be used a time. The communication channel could be varied during the normal working Mode to realize a multifrequency communication. Selecting the desired frequency in the Control Register the Transmission and Reception filters are accordingly tuned. Table 1. FCarrier F0 F1 F2 F3 F4 F5 F6 F7(1) F (KHz) 60 66 72 76 82.05 86 110 132.5 Baud Rates ST7538 is a multi Baud rate device: four Baud Rate are available (See table 2). Table 2. Baud Rate [Baud] 600 1200 2400(1) 4800 Note: 1. 2. 3. 4. Default value Frequency deviation. Deviation = F / (Baud Rate) Deviation 0.5 Not Allowed F (2)(Hz) 600 600 1200 1200(1) 2400 2400 4800 Deviation (3) 1(4) 0.5 1 0.5 1 0.5 1 9/30 ST7538 Mark and Space Frequencies Mark and Space Communication Frequencies are defined by the following formula: F ("0") = FCarrier + [F]/2 F ("1") = FCarrier - [F]/2 F is the Frequency Deviation. With Deviation = "0.5" the difference in terms of frequency between the mark and space tones is half the Baudrate value (F=0.5*BAudrate). When the Deviation = "1" the difference is the Baudrate itself (F= Baudrate). The minimal Frequency Deviation is 600Hz. Table 3. Carrier Frequency (KHz) 60 Baud Rate 600 1200 2400 4800 66 600 1200 2400 4800 72 600 1200 2400 4800 76 600 1200 2400 4800 Deviation -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 75684 75684 75358 75358 74870 74870 73568 76335 76335 76660 76660 77148 77148 78451 4800 2400 1200 71777 71777 71452 71452 70801 70801 69661 72266 72266 72591 72591 73242 73242 74382 132.5 600 4800 2400 1200 65755 65755 65430 65430 64779 64779 63639 66243 66243 66569 66569 67220 67220 68359 110 600 4800 2400 1200 59733 59733 59408 59408 58757 58757 57617 60221 60221 60547 60547 61198 61198 62337 86 600 4800 2400 1200 Exact Frequency [Hz] (Clock=16MHz) "1" "0" Carrier Frequency (KHz) 82.05 Baud Rate 600 Deviation -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 -1 0.5 1 0.5 1 0.5 1 132161 132161 131836 131836 131348 131348 130046 132813 132813 133138 133138 133626 133626 134928 109701 109701 109375 109375 108724 108724 107585 110352 110352 110677 110677 111165 111165 112467 85775 85775 85449 85449 84798 84798 83659 86263 86263 86589 86589 87240 87240 88379 81706 81706 81380 81380 80892 80892 79590 82357 82357 82682 82682 83171 83171 84473 Exact Frequency [Hz] (Clock=16MHz) "1" "0" 10/30 ST7538 Host Processor Interface ST7538 exchanges data with the host processor thorough a serial interface. The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged using RxD, TxD and CLR/T lines. s s s s Four are the ST7538 working modes: Data Reception Data Transmission Control Register Read Control Register Write REG_DATA and RxTx lines are level sensitive inputs. Table 4. REG_DATA Data Transmission Data Reception Control Register Read Control Register Write 0 0 1 1 RxTx 0 1 1 0 s Mains Access ST7538 features two type of communication interfaces: - Asynchronous - Synchronous The selection can be done through the internal Control Register. Figure 1. Asynchronous Data Interface RxD TxD RxTx CLR/T REG_DATA Synchronous Data Interface RxD TxD RxTx CLR/T REG_DATA Host Controller ST7538 Host Controller D03IN1415 ST7538 - Asynchronous Mode. ST7538 allows to interface the Host Controller using a 3 line interface (RXD,TXD & RxTx). Data are exchange without any auxiliary Clock reference in an Asynchronous mode without adding any protocol bits. The host controller has to recover the clock reference in receiving Mode and control the Bit time in transmission mode. RxD line is forced to a low logic level when no carrier is detected. 11/30 ST7538 - Synchronous mode. ST7538 allows to interface the host Controller using a four lines synchronous interface (RXD,TXD, CLR/T & RxTx). ST7538 is always the master of the communication and provides the clock reference on CLR/T line. When ST7538 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge. When ST7538 is in transmitting mode the clock reference is internally generated and data are read on TxD line on CLR/T rising Edge. If RxTx line is set to "1" & REG_DATA="0" (Data Reception), ST7538 enters in an Idle State and CLR/T line is forced Low. After Tcc time the modem starts providing received data on RxD line. If RxTx line is set to "0" & REG_DATA="0" (Data Transmission), ST7538 d in an Idle State and transmission circuitry is switched on. (figure 3). After Tcc time the modem starts transmitting data present on TXD line (figure 3) . Figure 2. Receiving Bit Synchronization Transmitting Bit Synchronization CLR/T CLR/T RxD TxD TS D03IN1416 TH Figure 3. Data Reception -> Data Transmission -> Data reception TCC CLR_T TB RXD REG_DATA TCR RxTx TS TH BIT22 D03IN1402 TCC TDS TDH TCR TXD BIT23 PACKET MODE (Only for Reception) In Packet mode data transmission from ST7538 to Host Controller is done at a higher speed than the Mains one. This function could reduce the efficiency of data exchange process because the Host Controller is involved in data reception for a shorter period of time. To achieve this function is enabled an internal auxiliary buffer which stores the incoming bits. The buffer is transferred to the host controller when full at the packet rate. The packet rate is programmable and is related to the Mclk clock frequency. The length of the packet can be also programmed through the control register (see table 9) to be 16, 14, 9 or 8 bits. The packet mode to start working needs two levels of enable. One at the control register level the other at the pin level. TxD is the pin that if forced High enables the Packet Mode Function. According to when TxD is forced high, the next incoming bit is stored inside the internal buffer or delivered on RxD pin. If TxD pin is forced low during a RX session the transceiver starts working in bit mode and the content of the packet buffer is deleted. 12/30 ST7538 Figure 4. Packet Mode Timing CLR_T TDS RXD TCRP TXD D03IN1406 TDH IDLE IDLE IDLE CLR_T RXD Control Register Access The communication with ST7538 Control Register is always synchronous. The access is achieved using the same lines of the Mains interface (RxD, TxD and CLR/T) plus REG_DATA Line. With REG_DATA = 1 and RxTx=0, the data present on TxD are loaded into the Control Register MSB first. The ST7538 sampled the TxD line on CLR/T rising edges. The control Register content is updated at the end of the register access section (REG_DATA falling edge). If more than 24 bits are transferred to ST7538 only the latest 24 bits are stored inside the Control Register. With REG_DATA = 1 and RxTx=1, the content of the Control Register is sent on RxD port. The Data on RxD are stable on CLR/T rising edges MSB First. 13/30 ST7538 Figure 5. Data Reception Control Register read Data Reception Timing Diagram TCC TCC TDS TDH BIT22 TCR TB CLR_T TDS RXD TCR TDH BIT23 REG_DATA RxTx D03IN1404 Figure 6. Data Reception CLR_T TDS RXD TDH Control Register write TCC Data Reception Timing Diagram TCC TB TCR REG_DATA TCR RxTx TS TXD TH BIT22 TCR TCR BIT23 D03IN1403 Figure 7. Data Transmission Control Register read Data Reception Timing Diagram TCC CLR_T TB RXD BIT23 TDS TDH TDS TDH TCC BIT22 REG_DATA TCR TCR TCR RxTx TS TXD D03IN1405 TH Figure 8. Data Transmission Control Register Write Data Reception Timing Diagram TCC CLR_T TB TXD TS REG_DATA TCR TCR RxTx TDS RXD D03IN1401 TCC TS TH BIT22 TCR BIT23 TH TDH 14/30 ST7538 Receiving Mode The receive section is active when RxTx Pin ="1" and REG_DATA=0. The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass Filter (+-10KHz). The Pre-Filter can be removed setting one bit in the Control Register. The Input Stage features a wide dynamic range to receive Signal with a Very Low Signal to Noise Ratio. The Amplitude of the applied waveform is automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (+-6K). The resulting signal is down-converted by a mixer using a sinewave generated by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter) improves the Signal to Noise ration before sending the signal to the FSK demodulator. The FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal Jitter. RxD Line is forced at logic level "0" when neither mark or space frequencies are detected on RAI Pin. Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct demodulation. While ST7538 is in Receiving Mode (RxTx pin ="1"), the transmit circuitry, Power Line Interface included, are turned off. This allows the device to achieve a very low current consumption (5 mA typ). In Receiving mode ATOP2 pin is internally connected to PAVSS. s High Sensitivity Mode It is possible to increase ST7538 Receiving Sensitivity setting to "1" the High Sensitivity Bit of Control Register. This Function allows to increase the communication reliability when the ST7538 sensitivity is the limiting factor. s Synchronization Recovery System (PLL) ST7538 embeds a Clock Recovery System to feature a Synchronous data exchange with the Host Controller. The clock recovery system is realized by means of a second order PLL. Data on the data line (RxD) are stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions LOCK-IN Range). The PLL Lock-in and Lock-out Range is /2. When the PLL is in the unlock condition, CLR/T and RxD lines are forced to a low logic level. When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the CLR/T Jitter. ST7538 PLL is forced in the un-lock condition, when more than 32 equal symbols are received. Figure 9. CLR/T RxD D03IN1417 LOCK-IN RANGE 15/30 ST7538 s Carrier/Preamble Detection The Carrier/Preamble Block is a digital Frequency detector Circuit. It can be used to manage the MAINS access and to detect an incoming signal. Two are the possible setting: - Carrier Detection - Preamble Detection CARRIER DETECTION: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RAI Input a signal with an harmonic component close to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception sensitivity (1mVrms Typ. in Normal Sensitivity Mode). The CD_PD line is forced to a logic level low when a Carrier is detected. PREAMBLE DETECTION: The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols ("1010" or "0101" are the symbols sequences detected). CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range. To reinforce the effectiveness of the information given by CD_PD Block, a digital filtering is applied on Carrier or Preamble notification signal (See Control Register Paragraph). The Detection Time Bits in the Control Register define the filter performance. Increasing the Detection Time reduced the false notifications caused by noise on main line. The Digital filter adds a delay to CD_PD notification equal to the programmed Detection Time. When the carrier frequency disappears, CD_PD line is held low for a period equal to the detection time and then forced high. Figure 10. CD_PD Timing during RX TDCD TCD CD_PD RAI D03IN1418 Figure 11. Receiving Path Block Diagram RXFO 31 Bit 3,4 3 RxD Bit 3,4 &14-21 8 CLR/T PLL Low Pass DIGITAL FILTER FSK DEMODULAOR Band Pass IF FILTER LOCAL OSC Bit 0 -2 Carrier Detection Band Pass CHANNEL FILTER GAIN CONTROL Bit 3,4 MIXER AGC Band Pass PRE-FILTER Bit 0-2 Bit 23 32 RAI Bit 9 & 10 1 CD_PD Low Pass 9 BU Bit 12 & 13 CARRIER/ PREAMBLE DETECTION BAND IN USE D03IN1419 16/30 ST7538 Transmission Mode The transmit mode is set when RxTx Pin ="0" and REG_DATA Pin ="0". In transmitting mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data (TXD) enter synchronously or asynchronously to the FSK modulator. - Host Controller Synchronous Communication Mode: on CLR/T rising edge, TXD Line Value is read and sent to the FSK Modulator. ST7538 Manage the Transmission timing according to the BaudRate Selected - Host Controller Asynchronous Communication Mode: TXD data enter directly to the FSK Modulator.The Host Controller Manages the Transmission timing In both conditions no Protocol Bits are added by ST7538. The FSK frequencies are synthesized in the FSK modulator from a 16 MHz crystal oscillator by direct digital synthesis technique. The frequencies Table in different Configuration is reported in Table 3. The frequencies precision is same as external crystal one's. In the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. The transition between a symbol and the following is done at the end of the on-going half FSK sinewave cycle. Figure 12. Bit 7 & 8 TIMER 7 TOUT THERMAL SENSOR Bit 14 5 TxD DAC Band Pass D-TYPE FLIP FLOP 8 CLR/T ZERO CROSSING PLI FSK MODULATOR TRANSMISSION FILTER PLI 21 ATOP2 ALC PLI Bit 0-5 Bit 0-2 19 ATOP1 CURRENT LOOP 23 CL VOLTAGE LOOP 29 Vsense 24 ATO 15 ZCOUT CLR/T GENERATOR 16 ZCIN D03IN1420 17/30 ST7538 s Automatic Level Control (ALC) The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ). Two are the control loops acting to define the ALC gain: - A Voltage Control loop - A Current Control Loop The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense. The gain adjustment is related to the result of a peak detection between the Voltage waveform on Vsense and two internal Voltage references. - If Vsense < VCLTH - VCLHYST - If VCLTH - VCLHYST < Vsense < VCLTH + VCLHYST - If Vsense > VCLTH + VLC HYST The next gain level is increased by 1 step No Gain Change The next gain level is decreased by 1 step The Current control loop acts to limit the maximum Peak Output current inside ATOP1 and ATOP2. The current control loop acts through the voltage control loop decreasing the Output Peak-to-Peak Amplitude to reduce the Current inside the Power Line Interface. The current sensing is done by mirroring the current in the High side MOS of the Power Amplifier (not dissipating current Sensing). The Output Current Limit (up to 400mApeak), is set by means of an external resistor (RCL) connected between CL and PAVss. The resistor converts the current sensed into a voltage signal. The Peak current sensing block works as the Output Voltage sensing Block: - If V(CL) < CCL TH - CCLHYST - If CCLTH - CCLHYST < V(CL) < CCLTH + CCLHYST - If V(CL) > CCL TH + CLCHYST Voltage Control Loop Acting No Gain Change The next gain level is decreased by 1 step Figure 13 shows the typical connection of Current anVoltage control loops. Figure 13. Voltage and Current Feedback external interconnection Example ALC ATOP/ATO Vout VRPK R1 VOLTAGE LOOP Vsense 5.6nF R2 VCLHYST VCLTH CURRENT LOOP CL RCL AVss 100pF CCLHYST CCLTH 1.865V (Typ) D03IN1421 Voltage Control Loop Formula R1 + R2 VR PK -------------------- ( V CLT H VCL HY ST ) R2 18/30 ST7538 Table 5. Vout vs. R1 & R2 resistors value Vout (Vrms) 0.150 0.250 0.350 0.500 0.625 0.750 0.875 1.000 1.250 1.500 Vout (dBV) 103.5 108.0 110.9 114.0 115.9 117.5 118.8 120.0 121.9 123.5 (R1+R2)/R2 1.1 1.9 2.7 3.7 4.7 5.8 6.6 7.6 9.5 10.8 R2 (K) 7.5 5.1 3.6 3.3 3.3 2.7 2.0 1.6 1.6 1.6 R1 (K) 1.0 3.9 5.6 8.2 11.0 12.0 11.0 10.0 13.0 15.0 Notes: The rate of R2 takes in account the input resistance on the SENSE pin (36 K). 5.6nF capacitor effect has been neglected. Figure 14. Typical Output Current vs. Rcl Irms (mA) 325 300 275 250 225 200 175 150 125 100 2 2.5 3 3.5 4 4.5 5 D01IN1311 Rcl(K) s Integrated Power Line Interface (PLI) The Power Line Interface (PLI) is a double CMOS AB Class Power Amplifier with the two outputs (ATOP1 and ATOP2) in opposition of phase. Two are the possible configuration: - Single Ended Output (ATOP1). - Bridge Connection The Bridge connection guarantee a Differential Output Voltage to the load with twice the swing of each individual Output. This topology virtually eliminates the even harmonics generation. The PLI requires, to ensure a proper operation, a regulated and well filtered Supply Voltage. PAVcc Voltage must fulfil the following formula to work without clipping phenomena: PAVcc VATOP ( AC ) + 7.5V ----------------------------------2 To allow the driving of an external Power Line Interface, the output of the ALC is available even on ATO pin. ATO output has a current capability much lower than ATOP1 and ATOP2. 19/30 ST7538 Figure 15. PLI Bridge Topology VRPK INVERTER ATOP2 2*VRPK LOAD ATOP1 Vout ALC R1 VOLTAGE LOOP Vsense 5.6nF R2 VRPK CURRENT LOOP CL RCL PAVss 100pF D03IN1422 Figure 16. PLI Startup Timing Diagram RX/TX TALC TRXTX 4V TST ATOP2 0V STEP NUMBER 16 17 18 31 D03IN1408 20/30 ST7538 Control Register The ST7538 is a multi-channel and multifunction transceiver. An internal 24 Bits Control Register allows to manage all the programmable parameters (table 5). The programmable functions are: s Channel Frequency s s s s s s s s s s s s s s Baud Rate Deviation Watchdog Transmission Timeout Frequency Detection Time Zero Crossing Synchronization Detection Method Mains Interfacing Mode Output Clock Packet Mode Baudrate Packet Length Packet Enable Input Pre-Filter Sensitivity Mode 21/30 ST7538 Table 6. Control Register Functions Function 0 to 2 Frequencies 60 KHz 66 KHz 72 KHz 76 KHz 82.05 KHz 86 KHz 110 KHz 132.5 KHz 3 to 4 Baud Rate 600 1,200 2,400 4,800 5 Deviation 0.5 1 6 Watchdog Disabled Enabled (1.5 s) 7 to 8 Transmission Time Out Bit 8 Disabled 1s 3s Not Used 0 0 1 1 Bit 10 500 s 1 ms 3 ms 5 ms 0 0 1 1 Bit 11 Disabled Enabled 0 1 Disabled Value Selection Bit2 0 0 0 0 1 1 1 1 Bit 4 0 0 1 1 Bit 5 0 1 Bit 6 0 1 Bit 7 0 1 0 1 Bit 9 0 1 0 1 1 ms 1 sec Enabled 0.5 Bit1 0 0 1 1 0 0 1 1 Bit0 0 1 0 1 0 1 0 1 Bit 3 0 1 0 1 2400 132.5 kHz Note Default 9 to 10 Frequency detection time 11 Zero Crossing Synchronization 22/30 ST7538 Table 6. Control Register Functions (continued) Function Value Selection Bit 13 12 to 13 Detection Method Carrier detection without conditioning 0 Bit 12 0 Carrier Detection Notification on CD_PD Line CLR/T and RxD signal always Present CLR/T and RxD lines are forced to "0" when Carrier is not detected Preamble Detection Notification on CD_PD Line CLR/T and RxD signal always Present Preamble Detection Notification on CD_PD Line CLR/T and RxD lines are forced to "0" when Preamble has not been detected or PLL is in Unlock condition Preamble detection without conditioning Note Default Carrier detection with conditioning Preamble detection without conditioning 0 1 1 0 Preamble detection with conditioning 1 1 Bit 14 14 Mains Interfacing Mode Synchronous Asynchronous Bit 16 15 to 16 Output Clock 16 MHz 8 MHz 4 MHz Not Used 0 0 1 1 Bit 18 17 to 18 Packet Mode Baud Rate Mclk/32 Mclk/64 Mclk/128 Mclk/256 0 0 1 1 Bit 20 19 to 20 Packet Length 8 Bit 9 Bit 14 Bit 16 Bit 0 0 1 1 Bit 21 21 Packet Mode Enable Disabled Enabled 0 1 Bit 22 22 Sensitivity Mode Normal Sensitivity High Sensitivity 0 1 Bit 23 23 Input Filter Disabled Enabled 0 1 Disabled Normal Disabled 0 1 Bit 15 0 1 0 1 Bit 17 0 1 0 1 Bit 19 0 1 0 1 14 bits MLCK/64 4 MHz Asynchronous 23/30 ST7538 AUXILIARY ANALOG AND DIGITAL FUNCTIONS Band In Use The Band in Use Block has a Carrier Detection like function but with a different Input Sensibility (77dBV Typ.) and with a different BandPass filter Selectivity (40dB/Dec). BU line is forced High when a signal in band is detected. To prevent BU line false transition, BU signal is conditioned to Carrier Detection Internal Signal. Time Out Time Out Function is a protection against a too long data transmission. When Time Out function is enabled after 1 or 3 second of continuos transmission the transceiver is forced in receiving mode. This function allows ST7538 to automatically manage the CENELEC Medium Access specification. When a time-out event occur, TOUT is forced high, and is held high for at least 125 ms. To Unlock the Time Out condition RxTx should be forced High. During the time out period only register access or reception mode are enabled. During Reset sequence if RxTx line ="0" & REG_DATA line ="1", TIMEOUT protection is suddendly enabled and ST7538 must be configured in data reception after the reset event before starting a new data transmission. Time Out time is programmable using Control Register bits 7 and 8 (table 6). Figure 17. Time-out Timing and Unlock Sequence RxTx TOUT TOFF TOFFD TOUT D03IN1409 Reset & Watchdog RSTO Output is a reset generator for the application circuitry. During the ST7538 startup sequence is forced low. RSTO becomes high after a TRSTO delay from the end of oscillator startup sequence. Inside ST7538 is also embedded a watchdog function. The watchdog function is used to detect the occurrence of a software fault of the Host Controller. The watchdog circuitry generates an internal and external reset (RSTO low for TRSTO time) on expiry of the internal watchdog timer. The watchdog timer reset can be achieved applying a negative pulse on WD pin Fig 18. Figure 18. Reset and Watchdog Timing TRSTO TWO TRSTO RSTO TWD WD TWM D03IN1410 24/30 ST7538 Zero Crossing Detection The Mains Voltage Zero Crossing can be detected, through a proper connection of ZCIN to the Mains. ZCIN comparator has a threshold fixed at SGND. ZCOUT is a TTL Output forced High after a positive zero-crossing transition, and low after a negative one. Setting the Bit 11 inside the Control Register to "1" the transmission is automatically synchronized to the mains positive zero-crossing transition. This function is achieved turning on the PLI when RX/TX is low and delaying the CLR/T first transition until the first zero-crossing event. The automatic synchronization procedure can work only if the synchronous interface is programmed. If asynchronous interface is in use the Zero Crossing synchronization can be achieved managing the ZCOUT line. Figure 19. Synchronous Zero-Crossing Transmission ZCIN t RxTx CLR/T TxD ZCDEL ZCOUT D03IN1423 Output Clock MCLK is the master clock output. The clock frequency sourced can be programed through the control register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4). The transition between one frequency and another is done only at the end of the ongoing cycle. Reg OK REGOK allows to detect an undesired modification of the control register content. REGOK function is disabled during a control register writing session. Under Voltage Lock Out The UVLO function turns off the device if the PAVdd voltage falls under 4V. Hysteresis is 340mV typically. Thermal Shutdown The ST7538 is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170C 10% . Hysteresis is around 30C. When shutdown threshold is overcome, PLI interface is switched OFF. Thermal Shutdown event is notified to the HOST controller using TIMEOUT line. When TIMEOUT line is High, ST7538 junction temperature exceed the shutdown threshold (Not Lached). 5V Voltage Regulator and Power Good Function ST7538 has an embedded 5V linear regulator externally available to supply the application circuitry. The linear regulator has a very low quiescent current (50A) and a current capability of 100mA. The regulator is protected against short circuitry events. When the regulator Voltage is above the power good threshold (VPG), Power Good line is forced high, while is forced low at startup and when VDC falls below VPG - VPGHYS Voltage. 25/30 ST7538 Figure 20. Power Good Function VDC 4.5V 250mV Time PG PG OK D03IN1411 Time Power-Up Procedure To ensure ST7538 proper power-Up sequence, PAVcc, AVss and DVss Supply has to fulfil the following rules: PAVcc rising slope must not exceed 10V/ms. When DVdd and AVdd are below 5V: 100mV < PAVcc-AVdd , PAVcc-DVdd < 1.2V. When AVdd and DVdd supply are connected to VDC the above mentioned relation is guarantied if VDC load < 100mA and if the filtering capacitor on VDC < 100uF. Figure 21. Power-UP Sequence Voltage PAVcc 5V PAVcc-AVdd PAVcc-DVdd DVdd, AVdd D03IN1424 Time PACKAGE INFORMATION Best thermal performance is acheived when slug is soldered to PCB. It is recomended to have five solder dots (See fig. 22) without resist to connect the Copper slug to the ground layer on the soldering side. Moreover it is recomeded to connect the ground layer on the soldering side to another ground layer on the opposite side with 15 to 20 vias. It is suggested to not use the PCB surface below the slug area to interconnect any pin except groung pins. 26/30 N.C. N.C. SGND 17 22 40 38 37 21 24 32 LOAD ATOP1 R1 RAI ATO AC LINE ATOP2 No External Components for POWER LINE DRIVER C_MINUS C_PLUS C_OUT PAVCC SINGLE SUPPY AC/DC Converter 25 39 34 N.C. N.C. VDC 33 44 28 5V Supply for Host Controller DVdd 10 13 30 35 14 42 36 7 9 Vsense R2 15 1 3 5 4 8 31 16 27 11 12 20 PAVSS DVSS DVSS 18 2 GND 6 GND 41 26 43 RxFO ZCIN XIN Zero Crossing Transmission Synchronization XOUT RCL 23 CL 29 19 AVdd TEST3 TEST2 TEST1 WD PG REGOK TOUT BU ST7538 C1 ZCOUT HOST CONTROLLER RxD TxD CD/PD Voltage Regulation & Current Protection C2 RX/TX Figure 22. Application Schematic Example with Coupling Tranformer. CLR/T REG/DATA 5 Lines Serial Interface MCLK RSTO Clock & Reset for Host Controller ST7538 D03IN1412 27/30 ST7538 Figure 23. ST7538 Slug Drawing 0.10mm 0.05 Copper Slug Solder plated Lead frame D03IN1414 Figure 24. Soldering Information Cu plate Solder dots Package Sizes B A L L1 10x10x1.4mm 2.00 mm 1.00 mm 6.00 mm 10.00 mm A B L L1 (Copper plate) L L1 D03IN1413 If PCB with ground layer, connect copper plate with 15 to 20 vias 28/30 ST7538 mm DIM. MIN. A A1 A2 b c D D1 D3 e E E1 E3 H L L1 S S1 K ccc 6.00 6.00 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 0.80 12.00 10.00 8.00 5.89 0.60 1.00 0.236 0.236 0 (min.), 3.5 (typ.), 7(max.) 0.10 0.004 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.003 0.464 0.386 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.232 0.024 0.039 0.030 0.480 0.401 0.055 0.014 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch OUTLINE AND MECHANICAL DATA TQFP44 (10x10x1.40mm) with Slug Down 0049510 D 29/30 ST7538 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 30/30 |
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